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Archive: https://archive.today/OB6FQ

From the post:

>A new chip architecture from IBM can integrate nearly 100 billion transistors on a chip the size of a human fingernail—nearly twice the transistor density of the company’s previous generation of chip technology. The resulting improvement in chip compute performance and energy efficiency comes from what IBM describes as the “world’s first sub-1 nanometer chip technology” for AI data centers.

Archive: https://archive.today/OB6FQ From the post: >>A new chip architecture from IBM can integrate nearly 100 billion transistors on a chip the size of a human fingernail—nearly twice the transistor density of the company’s previous generation of chip technology. The resulting improvement in chip compute performance and energy efficiency comes from what IBM describes as the “world’s first sub-1 nanometer chip technology” for AI data centers.
[–] • 2 pts

Wild. If you understand the tech and physical limits this is worm hole territory, quantum tunneling? The charges between the 'walls' of a circuit, which are so incredibly narrow, get so unstable that electrons simply ignore the physical barriers entirely. Instead of staying confined inside the channel, they seamlessly teleport through the atom-thin gate walls via quantum tunneling, causing massive current leakage, wasting power, and making it nearly impossible to turn the transistor 'off' reliably.

bold part is AI, full disclosure because I'm only 63% nigger.

[–] • 1 pt

This sounds like a feature for ai….you can’t turn it off.

[–] • 1 pt

Some kinetic energy to the chips will help turn them off.

[–] • 0 pt (edited )

That's because the "sub 1nm technology" claim is pure bullshit.

The chip industry stopped being honest with that metric way back in 2001. It no longer measures the gate length at all (the original honest metric).

This chip is marketed as "sub 1nm" because it's "equivalent" to that in a marketing person's mind.

In reality it's got multiple layers. They've gotten the actual gate length down to about 7nm. The physical limit is about 3nm before quantum tunneling ends our ability to shrink silicon transistors.