this whole conversation is about controller chips I am saying RISC-V cannot be used for any normal functions yet, until 500,000 dollars is paid to a engineer to design and fab a clean FPGA to perform I/O for the motherboard, and no one in RISC-V did that yet the many times I checked. The DMA used allowing direct RAM ream/write of cached ram layers by attached chips on circuit-board are regularly infested by Chinese/Israelis/NSA via hidden code in microcode of ARM cores burnt onto USB and SATA controller chips. These USB and SATA controller chips look for data flying through them (jpeg streams, png, etc) that have special data patterns that then activate and warm program the USB and SATA controller chips to perform certain functions as PCI "busmasters" when they are granted bus master status periodically. The USB and SATA controller chips can READ and WRITE anywhere in RAM!!!! they can root and infect a RISC-V motherboard trivially by modifying any flashable storage anywhere (microcode cpu at boot, keyboard, etc) I could do it, but have no interest arguing with subverting shills in the RISC-V community that have low IQ or no idea how often raping a machine via controller chips happens. Firewire port raped macintoshes in the past, proven. SATA raped pcs in the past if AHCI (and they all were loose ACHI). USB is used to but rape All intel motherboards made since 4 years ago, and all amd from 2 or less years ago if a signed crypto key on microcode payload is accepted by the cpu. USB and SATA cannot in 2021 ever be used on a RISC-V. Happily, a person could in theory design a large static ram SSD trampoline on a home made pci 4 lane card that relays messages (data) without DMA full access to a attached samsung ssd or other untrusted nvme by making a PCI bridge. a motherboard is allowed to bridge PCI for the last 19 years up to 4 layers deep in a tree, but each device in the tree uses up a precious number of the 127 ids allowed total. this whole conversation is about controller chips The RISC-V cpu might not be kiked or subverted but it would just be a chip sitting on a desk doing nothing without some I/O controllers. you can subvert motherboards lots of ways including JTAG. JTAG? yes : Top Secret Intel Backdoor re-proven! 'Intel Visualization of Internal Signals Architecture (VISA)' 'Orange Mystery JTAG' access to TXE of SHIPPED Intel support chips IIRC CS(TXE/ME) [and CPU] allows re-enable of 'VISA' Spy mode, so that USB sticks can suck crypto keys and passwords from RAM of running PCs! Intel VISA Exploit Gives Access to Computer’s Entire Data (from a USB dongle by a nighttime Janitor in your office), Researchers Show : JTAG harness required in latest chips to open old VISA exploit up though. : https://gadgets.ndtv.com/laptops/news/intel-visa-sa-00086-exploit-researchers-computer-data-access-2014854 Link to a Great discussions so far on this shocking news https://news.ycombinator.com/item?id=19535059 THIS IS DEVASTATING for pre 2018 Intel chips and if pc tampered with (JTAG clip or JTAG spy chip on motherboard), is devastating for 2019 Intel CPUs too! In this case the usb protocol on a support chip looks for "secret sauce" when cpu prior enabled for hardware debug probe by a "evil maid" and the stick can deliver code to cpu to do things on a sleeping "LOCKED" but booted pc. Other intel stuff of the past like "Management Engine" did so when machine powered off but in low power 5 volt "ready wake" mode. But ASICS anywhere on board in this exploit that have JTAG (all do) can use JTAG to force a 2019 Intel CPU to use the "ME" to reconfigure the main CPU back to "exploit spy mode" or <ahem> hardware debug mode via USB. But only a CPU and cache controller has access to all RAM pages in a normal design unless the are granted "BUS GRANT" signal. Getting "BUS GRANT" is not a lot more than a pci controller asserting a set of wires in a pattern... BUT the current master has to CEDE, and secure OS (any OS) might not cede when in a certain state such as not servicing code modded to a driver of such originating bus grant request. It is possible to re-fetch a prior cache-line back from RAM mapped to pci devices space, without a full bus grant, but that is no big deal, and not a lot of RAM exposure.